.\" -*- mode: troff; coding: utf-8 -*-
.\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43)
.\"
.\" Standard preamble:
.\" ========================================================================
.de Sp \" Vertical space (when we can't use .PP)
.if t .sp .5v
.if n .sp
..
.de Vb \" Begin verbatim text
.ft CW
.nf
.ne \\$1
..
.de Ve \" End verbatim text
.ft R
.fi
..
.\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>.
.ie n \{\
.    ds C` ""
.    ds C' ""
'br\}
.el\{\
.    ds C`
.    ds C'
'br\}
.\"
.\" Escape single quotes in literal strings from groff's Unicode transform.
.ie \n(.g .ds Aq \(aq
.el       .ds Aq '
.\"
.\" If the F register is >0, we'll generate index entries on stderr for
.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index
.\" entries marked with X<> in POD.  Of course, you'll have to process the
.\" output yourself in some meaningful fashion.
.\"
.\" Avoid warning from groff about undefined register 'F'.
.de IX
..
.nr rF 0
.if \n(.g .if rF .nr rF 1
.if (\n(rF:(\n(.g==0)) \{\
.    if \nF \{\
.        de IX
.        tm Index:\\$1\t\\n%\t"\\$2"
..
.        if !\nF==2 \{\
.            nr % 0
.            nr F 2
.        \}
.    \}
.\}
.rr rF
.\" ========================================================================
.\"
.IX Title "OPENSSL_ia32cap 3"
.TH OPENSSL_ia32cap 3 2019-12-20 1.0.2u OpenSSL
.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
.if n .ad l
.nh
.SH NAME
OPENSSL_ia32cap, OPENSSL_ia32cap_loc \- the IA\-32 processor capabilities vector
.SH SYNOPSIS
.IX Header "SYNOPSIS"
.Vb 2
\& unsigned long *OPENSSL_ia32cap_loc(void);
\& #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
.Ve
.SH DESCRIPTION
.IX Header "DESCRIPTION"
Value returned by \fBOPENSSL_ia32cap_loc()\fR is address of a variable
containing IA\-32 processor capabilities bit vector as it appears in
EDX:ECX register pair after executing CPUID instruction with EAX=1
input value (see Intel Application Note #241618). Naturally it's
meaningful on x86 and x86_64 platforms only. The variable is normally
set up automatically upon toolkit initialization, but can be
manipulated afterwards to modify crypto library behaviour. For the
moment of this writing following bits are significant:
.IP "bit #4 denoting presence of Time-Stamp Counter." 4
.IX Item "bit #4 denoting presence of Time-Stamp Counter."
.PD 0
.IP "bit #19 denoting availability of CLFLUSH instruction;" 4
.IX Item "bit #19 denoting availability of CLFLUSH instruction;"
.IP "bit #20, reserved by Intel, is used to choose among RC4 code paths;" 4
.IX Item "bit #20, reserved by Intel, is used to choose among RC4 code paths;"
.IP "bit #23 denoting MMX support;" 4
.IX Item "bit #23 denoting MMX support;"
.IP "bit #24, FXSR bit, denoting availability of XMM registers;" 4
.IX Item "bit #24, FXSR bit, denoting availability of XMM registers;"
.IP "bit #25 denoting SSE support;" 4
.IX Item "bit #25 denoting SSE support;"
.IP "bit #26 denoting SSE2 support;" 4
.IX Item "bit #26 denoting SSE2 support;"
.IP "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
.IX Item "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;"
.IP "bit #30, reserved by Intel, denotes specifically Intel CPUs;" 4
.IX Item "bit #30, reserved by Intel, denotes specifically Intel CPUs;"
.IP "bit #33 denoting availability of PCLMULQDQ instruction;" 4
.IX Item "bit #33 denoting availability of PCLMULQDQ instruction;"
.IP "bit #41 denoting SSSE3, Supplemental SSE3, support;" 4
.IX Item "bit #41 denoting SSSE3, Supplemental SSE3, support;"
.IP "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);" 4
.IX Item "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
.IP "bit #57 denoting AES-NI instruction set extension;" 4
.IX Item "bit #57 denoting AES-NI instruction set extension;"
.IP "bit #59, OSXSAVE bit, denoting availability of YMM registers;" 4
.IX Item "bit #59, OSXSAVE bit, denoting availability of YMM registers;"
.IP "bit #60 denoting AVX extension;" 4
.IX Item "bit #60 denoting AVX extension;"
.IP "bit #62 denoting availability of RDRAND instruction;" 4
.IX Item "bit #62 denoting availability of RDRAND instruction;"
.PD
.PP
For example, clearing bit #26 at run-time disables high-performance
SSE2 code present in the crypto library, while clearing bit #24
disables SSE2 code operating on 128\-bit XMM register bank. You might
have to do the latter if target OpenSSL application is executed on SSE2
capable CPU, but under control of OS that does not enable XMM
registers. Even though you can manipulate the value programmatically,
you most likely will find it more appropriate to set up an environment
variable with the same name prior starting target application, e.g. on
Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or
better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same
effect without modifying the application source code. Alternatively you
can reconfigure the toolkit with no\-sse2 option and recompile.
.PP
Less intuitive is clearing bit #28. The truth is that it's not copied
from CPUID output verbatim, but is adjusted to reflect whether or not
the data cache is actually shared between logical cores. This in turn
affects the decision on whether or not expensive countermeasures
against cache-timing attacks are applied, most notably in AES assembler
module.
.PP
The vector is further extended with EBX value returned by CPUID with
EAX=7 and ECX=0 as input. Following bits are significant:
.IP "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;" 4
.IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
.PD 0
.IP "bit #64+5 denoting availability of AVX2 instructions;" 4
.IX Item "bit #64+5 denoting availability of AVX2 instructions;"
.IP "bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL and RORX;" 4
.IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL and RORX;"
.IP "bit #64+18 denoting availability of RDSEED instruction;" 4
.IX Item "bit #64+18 denoting availability of RDSEED instruction;"
.IP "bit #64+19 denoting availability of ADCX and ADOX instructions;" 4
.IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"